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Presentation On Electronic Devices

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Published in: Electronics
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Comparators, ADC, DAC, Summer, Integrator

Nithya P / Ajman

5 years of teaching experience

Qualification: B Tech in Electronics And Communication Engineering, MBA in E Business

Teaches: Electronics, Physics, Engineering, Electrical Technology, Chemistry, Computer Science, Maths, Mathematics

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  1. Electronic Devices Ninth Edition Floyd LO-3.2 ELE-3413: Electronics-Il
  2. Sum"/ Comparators A comparator is a specialized nonlinear op-amp circuit that compares two input voltages and produces an output state that indicates which one is greater. Comparators are designed to be fast and frequently have other capabilities to optimize the comparison function. An example of a comparator application is shown. The circuit detects a power failure in order to take an action to save data. As long as the comparator senses Vin, the output will be a dc level. Comparator Differentiator Retriggerable one-shot
  3. (a) Battery reference Comparators (b) Voltage-divi&r reference (d) Waveforms (c) Zetrr diode sets reference voltage
  4. Effects of Noise on Comparators < FIGURE 13-6 Effects of noise on comparator circuit. (a) (b)
  5. Sum"/ Comparator with Hysteresis Sometimes the input signal to a comparator may vary due to noise superimposed on the input. The result can be an unstable output. To avoid this, hysteresis can be used. Hysteresis is incorporated by adding regenerative (positive) feedback, which creates two switching points: the upper trigger point (UT P) and the lower trtgger point (LTP). After one trigger point is crossed, it becomes inactive and the other one becomes active. VUTP o (max) — o m (max)
  6. Comparator with Hysteresis Equation 13—1 (a) When the output is at the maximum positive voltage and the input exceeds UTP, the output switches to the maximum negative voltage. 0 — o M (max) VUTP out (max)) (b) When the output is at the maximum negative voltage and ttæ input below [TR the output switches back to the maximum positive voltage.
  7. Sum"/ Comparator with Hysteresis A comparator with hysteresis is also called a Schmitt trigger. The trigger points are found by applying the voltage-divider rule: and VLTP UTP Out Out ( Example; What are the trigger points for the circuit if the maximum output is V? solution: IOkQ (+13 V) UTP 47 kQ+ 10 kQ = 2.28 v By symmetry, the lower trigger point — - -2.28 v. 47 kQ 10 Q
  8. Sum"/ Output Bounding Some applications require a limit to the output of the comparator (such as a digital circuit). The output can be limited by using one or two zener diodes in the feedback circuit. The circuit shown here is bounded as a positive value equal to the zener breakdown voltage. 0 _0.7V
  9. Output Bounding Bounded at a negative value +0.7 v +0.7 v 0.7 v
  10. Solution Determine the output voltage waveform for Figure 13—13. This comparator has both hysteresis and zener bounding. The voltage across DI and in either direction is 4.7 V + 0.7 V = 5.4 V. This is because one zener is always forward-biased with a drop of 0.7 V when the other one is in breakdown. 4.7 v 0 4.7 V IOOkO 47 k-n The voltage at the inverting (—) op-amp input is v our ± 5.4 V. Since the differen- tial voltage is negligible, the voltage at the noninverting (+) op-amp input is also approximately v out + 5.4 V. Thus, (Vow ± 5.4 V) = +5.4 V VRI = VRI +5.4 V — 54 100 kn Since the noninverting input current is negligible, IR2 = IRI = +54 gA +2.54V + — +5.4 V ± 2.54 V - +7.94 V
  11. The upper trigger point (UTP) and the lower trigger point (LTP) are as follows: (+1/ out) — ( — V out) = LTP = 47kQ (+7.94 V) = +2.54 V 147 kO 47 kO (-7.94 v) = -2.54 v 147 kQ The output waveform for the given input voltage is shown in Figure 13—14. FIGURE 13-14 +2.54 v -2.54 v +7.94 v _7.94 V
  12. Sum"/ Comparator Applications Simultaneous or flash analog-to-digital converters use 217-1 comparators to convert an analog input to a digital value for processing. Flash ADCs are a series of comparators, each with a slightly different reference voltage. The priority encoder produces an output equal to the highest value input. In IC flash converters, the priority encoder usually includes a latch that holds the converter data constant for a period of time after the conversion. Priwity
  13. ADC Converter Determine the binary number sequence of the three-digit simultaneous ADC in Figure 13—16 for the input signal in Figure 13—17 and the sampling pulses (encoder enable) shown. Draw the resulting digital output waveforms. FIGURE 13-11 Sampling of values on analog waveform for conversion to digital. Solution 8 6 1 2 3 4 5 6 7 s 9 10 11 12 Encexjer (sampling pulses) The resulting binary cultput sequence is listed as follows and is shown in the waveform diagram Of Figure 13—18 in relation to the sampling pulses. 011.101. 110, 110, 100, 001.000.001,010. 101, 110. Ill
  14. ADC Converter c. FIGURE 13-18 Resulting digital outputs for sampled values in Figure 13—17. Do is the least significant digit. Encoder enable pulses 1 2131 4 5 1617 010 819 110111 112 010 Ill Il 0 o Ill Ill 01010 10
  15. Sum"/ Summing Amplifier A summing amplifier has two or more inputs; normally all inputs have unity gain. The output is proportional to the negative of the algebraic sum of the inputs. Example What is v OUT if the input voltages are +5.0 V, —3.5 V and +4.2 V and all 2 resistors = 10 kQ? Solution; V OUT = _(VINI + VIN2 + VIN 3) = -(+5.0 v - 3.5 v + 4.2 V) = -5.7 v RI R. 10kQ
  16. Sum"/ Averaging Amplifier An averaging amplifier is basically a summing amplifier with the gain set to R /R = l/n (n is the number of inputs). The output is the negative average of the inputs. Example; What is Soluti011; if the input voltages are +5.0 V, —3.5 V and +4.2 V? Assume 3.3kQ VOUT — —1/3(VINl + VIN2 + VIN3) - -1/3(+5.0 v - 3.5 v + 4.2 V) = -1.9 v 3
  17. Sum"/ Scaling Adder A scaling adder has two or more inputs with each input having a different gain. The output represents the negative scaled sum of the inputs. Example; Assume you need to sum the inputs from three microphones. The first two microphones require a gain of —2, but the third microphone requires a gain of —3. What are the values of the input R 's if R = 10 kQ? solution; 10 kQ IOkQ = 5.0kQ 10kQ = 3.3kQ
  18. Sum"/ Scaling Adder An application of a scaling adder is the D/A converter circuit shown here. The resistors are inversely proportional to the binary column weights. Because of the precision required of resistors, the method is useful only for small DACs. 4R 21 OUT
  19. EXAMPLE 13-9 .02 (a) DAC Converter Determine the output voltage of the DAC in Figure 13—27(a). The sequence of four- digit binary codes represented by the waveforms in Figure are applied to the inputs. A high level is a binary 1 , and a low level is a binary 0. The least significant bi- nary digit is Do. 200 kn 100 kn 50 kn 25 o FIGURE 13-27 0123456789101112131415 (b) Solution First, determine the current for each of the weighted inputs. Since the inverting input of the oramp is at 0 V (virtual ground) and a binary I corresponds to a high level (+5 V), the current through any of the input resistors equals 5 V divided by the resistance value.
  20. - 0.025mA 200 kn = 0.05 mA 100kQ 12 = = 0.1 mA 50kQ = 0.2 mA 25kQ There is almost no current at the inverting op•amp input because Of its extremely high imß•dance. Therefore, assume that all of the input current is through Rt. Since one end of R, is at 0 V (virtual ground). the drop across RJ equals the output voltage, which is negative with respect to virtual ground. -Rflo = = -0.25 V RHI — DAC Converter VOUT(DI' — — VOUT(D2' = — Vourcmj — — — —o.sv B input -0.75 v•av)
  21. Sum"/ R/2R Ladder DAC A more widely used method for D/A conversion is the R/2R ladder. The gain for is —l. Each successive input has a gain that is half of previous one. The output represents a weighted sum of all of the inputs (similar to the scaling adder). An advantage of the R/2R ladder is that only two values of resistors are required to implement the circuit. Inputs
  22. FAuivalent ladder resistance with D2, Dl. and Do grounded (a) F,quivalent circuit for Ih=o (b) Equivalent circuit for = O, R/2R Ladder DAC REQ=2R + 2.5 v I,D,— 2.5 v 2.5 v 25V
  23. R/2R Ladder DAC N = -125 V (c) Equivalent circuit for D-, DZ O, D, = l. Do— O (d) Ex?uivalent circuit for O, = O. Dl — O, Do I RTH R 1.25 v 0,625 v R 1-0 -IRf 0,625 _0625 v
  24. Sum"/ The Integrator The ideal integrator is an inverting amplifier that has a capacitor in the feedback path. The output voltage is proportional to the negative integral (running sum) of the input voltage. Op-amp integrating circuits must have extremely low dc offset and bias currents, because small errors are equivalent to a dc input. The ideal integrator tends to accumulate these errors, which moves the output toward saturation. The practical integrator overcomes these errors— the simplest method is to add a relatively large feedback resistor. Ideal Integrator Practical Integrator
  25. Sum"/ The Integrator If a constant level is the input, the current is constant. The capacitor charges from a constant current and produces a ramp. The slope of the output is given by the equation: AVo„ Example Sketch the output wave: At +2.0 v Vin O V 0.0 -2.0 v AVON (ms) 05 1.0 15 2.0 220kQ 0.1gF At Ric (10 PF) 10kQ +1.0 v -1.0 v 0.5 1.0 1.5 t (ms) 2.0
  26. Sum"/ The Integrator The result from the previous example can be confirmed with Multisim. This i the portion show on the 220kQ 0.1gF 8 S 48 m V 10kQ T2-Tl LOOO s 5000 ms 705,767 51100 ms 705.767 pv 500 Nor.
  27. Sum"/ The Differentiator The ideal differentiator is an inverting amplifier that has a capacitor in the input path. The output voltage is proportional to the negative rate of change of the input voltage. The small reactance of C at high frequencies means an ideal differentiator circuit has very high gain for high-frequency noise. To compensate for this, a small series resistor is often added to the input. This practical differentiator has reduced high frequency gain and is less prone to noise. Ideal Differentiator Practical Differentiator
  28. Sum"/ The Differentiator The output voltage is given by Vout Example: Sketch the output wave: Vin ov 0.0 -1.0 v 0.5 1.0 Solution; +20 v out OV 0.0 —2.0 v 0.5 ms t (ms) 2.0 10kQ 220 Q 0.1gF 10kQ 05 1.0 15 t (ms) 2.0
  29. Interactive4'1R&ïdl Op-Amp R/2R Ladder DAC Keeda
  30. Interactivöååf&jål Op-Amp Differentiator and Integrator Op-Amp as Integrator
  31. Interactivöååf&jål DAC op-amp based on scaling adder Binary Weighted Resistor DAC
  32. Interactivöååf&jål DAC op-amp based on scaling adder Binary Weighted Resistor DAC
  33. Selected Hysteresis Characteristics of a circuit in which two different trigger levels produce an offset or lag in the switching action. Schmitt trigger A comparator with built-in hysteresis. Bounding The process of limiting the output range of an amplifier or other circuit. Integrator A circuit that produces an output that approximates the area under the curve of the input function. Differentiator A circuit that produces an output that approximates the instantaneous rate of change of the input function.
  34. Qui///' 1. The signal that you would expect at the output of the comparator (red arrow) is a a. series of alternating positive and negative triggers b. sine wave c. square wave d. dc level Comparator Differentiator Retriggerable one-shot
  35. Qui///' 2. Hysteresis is incorporated in a comparator by adding a. a capacitor in series with the input b. capacitors from the power supply to ground c. a small resistor in series with the input d. positive feedback
  36. Qui///' 3. To find the trigger points for a Schmitt trigger, you can a. divide the saturation voltage by two b. apply Kirchhoff's Voltage Law c. apply the voltage-divider rule d. calculate the rate of change of the input
  37. Qui///' 4. A comparator output can be limited (bounded) by a. reversing the power supply voltages b. putting a zener diode in a feedback path c. decreasing the input resistance d. connecting the inverting input to ground
  38. Qui///' 5. Assume all resistors in the circuit shown here have the same value. The circuit is a 2 a. summing amplifier b. averaging amplifier c. scaling adder d. none of the above RI R.
  39. Qui///' 6. Assume all resistors in the circuit shown here have different values. The circuit is a 2 a. summing amplifier b. averaging amplifier c. scaling adder d. none of the above RI R.
  40. Qui///' 7. The circuit shown is a a. A/D converter b. R/2R ladder c. both of the above d. none of the above Inpu Ry=2R
  41. Qui///' 8. A practical integrator has a feedback resistor in parallel with C. The purpose of this resistor is to a. avoid noise b. increase the gain c. both of the above d. none of the above Practical Integrator
  42. Qui///' 9. A certain circuit has the input and output signals shown. The circuit is a. a differentiator b. an integrator c. a scaling amplifier d. none of the above +1.0 v in 0 V 0.0 -1.0 v 0.5 1.5 t(ms) 2.0 +2.0 v out 0 V 0.0 -2.0 v 1.0 15 t(ms) 2.0
  43. Qui///' 10. A differentiator circuit produces an output that is proportional to the negative of the a. sum of the inputs b. rate of change of the input c. area under the curve of the input d. none of the above
  44. Qui///' Answers: 10. b
  45. Homework Solve the following problems from the textbook. Chapter 13, Pages 711-714, Problems: 1, 2, 3, 4, 5, 9, 10, 13, 15, 16, 18

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